High performance complementary metal-oxide semiconductor (CMOS) very large scale integrated (VLSI) circuits are increasingly using dynamic logic gates to improve circuit performance. Dynamic logic gates are fast but require a frequent refresh to hold a logic state. Accordingly, because of the power and noise constraints on dynamic logic gates, many high performance CMOS VLSI must be designed with conventional static logic gates. Static circuits hold state without a frequent refresh. As power is consumed only when the inputs switch, static circuits consume less power. However, static circuits are generally slower than dynamic circuits. Hence, there is a current preference for dynamic gates in high performance circuits.
One solution is to mix static logic gates with dynamic logic gates. However, inasmuch as dynamic gates detect a pulse to sense a state while static gates sense an amplitude, it has been somewhat problematic to mix the two. That is, it has been difficult to provide circuit elements, particularly memory devices, which can generate and receive dynamic and static inputs.
In addition, the most area efficient dynamic gate implementations produce a single output that can not be easily complemented for those logic functions that require a "bar" or complemented signal. Also, certain manufacturing tests, such as scan testing, can not be used to verify the functionality of dynamic logic gates. Scan testing is an advantageous testing technique by which specific inputs and outputs are provided for the purpose of scan testing. However, scan testing is performed at much slower speeds than the operating speed of the circuit. During a scan test these inputs and outputs are interconnected and data is scanned in and read out. Scan testing can not be used with dynamic gates because the gates do not hold state but instead respond to pulses.
As the basic memory element in most logic is a flip-flop, there is a need in the art for a flip-flop that can accept or generate dynamic or static logic signals which can incorporate scan test logic circuitry.